USING FAST PROTOTYPING FACILITIES FOR IMPLEMENTATION OF A CONVOLUTION NEURAL NETWORK ON A FPGA
Abstract
Research in the field of artificial intelligence is carried out with increasing interest every year. The fields of application of artificial intelligence are quite extensive: automation, analysis of a large amount of data, smart home technology, machine vision, etc. Artificial intelligence technologies are based on the use of artificial neural networks, which are based on the principles of the animal nervous system. In this case, the actual issue is the implementation of artificial neural networks on various software and hardware platforms: programmable logic integrated circuits of the FPGA type (Field Programmable Gate Array), on special purpose integrated circuits (Application- Specific Integrated Circuit, ASIC), GPU, CPU etc. FPGA performs best in low-power mobile systems. ASIC demonstrates the highest performance at a fairly high development cost. The problem of rapid prototyping of projects based on the use of artificial neural networks for FPGAs using conventional methods (using HDL languages, HDL encoders, graphic programming) is that either such a project is complex and time-consuming to debug (HDL languages), or the resulting code is not optimal (HDL encoders), or the duration of the project development and the complexity of reconfiguring the neural network (graphical programming) are high. Therefore, in the framework of this work, an effective method for designing fully connected and convolutional neural networks for their implementation on FPGAs using the Xilinx System Generator for DSP and Matlab / Simulink package is considered. Artificial neural networks generated in this way are easily reconfigurable and allow solving the following problems: image recognition, optimal filtering (for example, for problems of subsurface radar).
References
ASIC [Development of hardware-oriented neural networks on FPGA and ASIC ], Vestnik
permskogo natsional'nogo issledovatel'skogo politekhnicheskogo universiteta. Elektrotekhnika,
informatsionnye tekhnologii, sistemy upravleniya [Bulletin of the Perm national research Polytechnic
University. Electrical engineering, information technology, management systems], 2019, No. 31.
2. Misra J., Saha I. Artificial neural networks in hardware: a survey of two decades of progress,
Neurocomputing, 2010, Vol. 74, No, 1-3, pp. 239-255.
3. Qiu, J., Song, S., Wang, Y., Yang, H., Wang, J., Yao, S., Xu, N. Going Deeper with Embedded
FPGA Platform for Convolutional Neural Network, Proceedings of the 2016 ACM/SIGDA International
Symposium on Field-Programmable Gate Arrays – FPGA ’16, 2016. DOI:
10.1145/2847263.2847265.
4. Alçın M., Pehlivan İ., Koyuncu İ. Hardware design and implementation of a novel ANN-based
chaotic generator in FPGA, Optik, 2016, Vol. 127, No. 13, pp. 5500-5505.
5. Solovyev R.A. et al. FPGA implementation of convolutional neural networks with fixed-point
calculations, Arxiv preprint arxiv:1808.09945, 2018.
6. Vorob'ev A.N., Shidlovskiy D.Yu., Bagrov A.A. Apparatnaya realizatsiya svertochnoy neyroseti
na PLIS s ispol'zovaniem model'no-orientirovannogo proektirovaniya [Hardware implementation
of convolutional neural network on FPGA using model-oriented design], Tsifrovaya
obrabotka signalov i ee primenenie – DSPA-2019 [Digital signal processing and its application-
DSPA-2019], 2019, pp. 423-429.
7. Bahoura M. FPGA implementation of an automatic wheezing detection system, Biomedical
Signal Processing and Control, 2018, Vol. 46, pp. 76-85. (bahoura2018.pdf).
8. Oniga S. A new method for FPGA implementation of artificial neural network used in smart
devices, International computer science conference microCAD, 2005, pp. 31-36.
9. Khodja D.E., Kheldoun A., Refoufi L. Sigmoid function approximation for ANN implementation
in FPGA devices, 2010.
10. Bakhchevnikov V.V. Elektrodinamicheskaya model' radiosignala, rasseyannogo na
mnogosloynoy strukture, s ispol'zovaniem fizicheskoy optiki i metoda trassirovki luchey
[Electrodynamic model of a radio signal scattered on a multilayer structure using physical optics
and ray tracing], Izvestiya vysshikh uchebnykh zavedeniy Rossii. Radioelektronika [News
of higher educational institutions of Russia. Radioelectronics], 2019, Vol. 22, No. 6.
11. Usenko O.A. Estimation of diagnostic significance of the control parameters of technological objects
based on graph model, Innovative technologies and didactics in teaching, 2017, pp. 67-73.
12. Romm YA.E., Belokonova S.S., Usenko O.A. Poisk i identifikatsiya ob"ektov razlichnykh tipov
na osnove priznakov ekstremal'nogo vida. II [Search for and identify various types of objects
based on extreme features. II], 2008.
13. Design M. B. D. S. P. Vivado Design Suite Reference Guide, 2012.
14. Matworks. Help Center. Add_block. Available at: https://www.mathworks.com/help/ simulink/
slref/add_block.html#d120e249911 (accessed 20.04.2020).
15. Kubat M. Neural networks: a comprehensive foundation by Simon Haykin, Macmillan, 1994,
ISBN 0-02-352781-7, The Knowledge Engineering Review, 1999, Vol. 13, No. 4, pp. 409-412.
16. Chang J., Sha J. An efficient implementation of 2D convolution in CNN, IEICE Electronics
Express, 2016б зз. 13.20161134.
17. Sibi P., Jones S. A., Siddarth P. Analysis of different activation functions using back propagation
neural networks, Journal of Theoretical and Applied Information Technology, 2013,
Vol. 47, No. 3, pp. 1264-1268.
18. Panicker M., Babu C. Efficient FPGA implementation of sigmoid and bipolar sigmoid activation
functions for multilayer perceptrons, IOSR J Eng., 2012, Vol. 2, pp. 1352-6.
19. Lobach V.T. i dr. Posledovatel'nyy sposob formirovaniya kanalov MIMO pri izmerenii
parametrov radiolokatsionnykh ob"ektov [Sequential method for forming MIMO channels
when measuring parameters of radar objects], Izvestiya YuFU. Tekhnicheskie nauki [Izvestiya
SFedU. Engineering Sciences], 2015, No. 11 (172), pp. 213-224.
20. Lu L. et al. Evaluating fast algorithms for convolutional neural networks on FPGAs, 2017
IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines
(FCCM). IEEE, 2017. pp. 101-108.
